CHIPS+ and Semiconductor Packaging
By: Hideki Tomoshige
Packaging—one of the final steps in semiconductor manufacturing—places chips in a protective case to prevent corrosion and to provide the interface that can combine and connect already made chips. To drive U.S. leadership in the $30.4 billion advanced semiconductor packaging market, the CHIPS and Science Act, signed into law in August 2022, calls on the National Institute for Standards and Technology (NIST) to establish a National Advanced Packaging Manufacturing Program (NAPMP). This follows the June 2021 100-day supply chain review ordered by the Biden administration of the risk posed by U.S. reliance on China and Taiwan for semiconductor packaging processes. Understanding these developments requires a closer look at the landscape for assembly, testing, and packaging (ATP).
The ATP Landscape
Semiconductor Packaging is an extremely labor-intensive process. To take advantage of lower wages and input costs, at least 81 percent of the world’s ATP production is located in Asia, according to the Boston Consulting Group and the Semiconductor Industry Association. There are two prevailing business models in the ATP market: Integrated Device Manufacturers (IDM) provide all semiconductor packaging processes in-house, while Outsourced Semiconductor Assembly and Test (OSAT) companies specialize in outsourced testing and assembly operations.
Currently, U.S. semiconductor firms offshore nearly all packaging processes to OSAT companies or rely on IDM facilities owned by U.S. companies that are located overseas. For example, Apple, which has a major chip design operation in the U.S., has an estimated $44.95 billion deal with Taiwanese semiconductor company ASE for ATP processes. According to the Bloomberg Terminal database, other U.S. semiconductor manufacturers, including Intel, Micron, and OnSemiconductor, also rely on major East Asian OSAT firms. In 2021, SEMI and Techsearch published a new edition of the Worldwide Assembly & Test Facility Database, which found that there were 373 total OSATs facilities worldwide in 2021, most of which were located in Asia, with 111 in China and 107 in Taiwan. Meanwhile, only 46 facilities were located in the U.S.
Similarly, for IDM facilities, the U.S. is dependent on China, Taiwan, and other Asian countries. For example, Texas Instruments, one of the leading global IDM companies in the U.S., has zero test and assembly/development facilities in the U.S. and transports all semiconductors that it manufactures in the U.S. to companies outside the U.S. for packaging. Meanwhile, Intel, another leading global IDM company based in the U.S., has only one such facility. As a result, Intel and Texas Instruments are 75 percent and 85 percent dependent on Asia, respectively, for ATP processes, with each company conducting about 30 percent of its packaging in China and Taiwan. This heavy reliance on companies in Asia, especially in China and Taiwan, is a weakness in the U.S. supply chain.
Amid growing Chinese assertiveness in technology policy and the disruptions in chip supply associated with the COVID-19 pandemic, a number of government and industry leaders are raising concerns about the exposure of the U.S. to supply disruptions in critical technologies. The NIST National Advanced Packaging Manufacturing Program represents a significant response to address this vulnerability.
Sustaining Moore’s Law
Packaging research is also seen as a way to remain on the cutting edge of semiconductor innovation. Historically, semiconductor research has focused on increasing the number of components on a single chip (“chip density”) in order to innovate smaller, higher performance, and multifunctional semiconductors. Companies such as Intel, TSMC, and Samsung compete on commercializing smaller, ever more advanced chips, sustaining Moore’s Law. As the technology bumps against the laws of physics, however, the quest for smaller chips is expected to yield less and less impact in terms of efficiency gains.
Innovations in chip packaging can raise the performance of electronic devices as well as lower the power consumption of chips. A focus on driving innovations in advanced packaging rather than just chip density can help make the U.S. semiconductor industry more competitive.
The National Advanced Packaging Manufacturing Program
NAPMP is tasked with building a robust domestic advanced packaging capability in the U.S. The CHIPS and Science Act, also known as CHIPS+, appropriates $11 billion over five years for research and development programs, including an initial $2.5 billion for the establishment of the NAPMP.
Under the NAPMP, NIST will bring together industry and academia to carry out shared research and innovation in high-performance, space-saving, and multi-functional packaging. This facility will provide companies with access to critical shared research infrastructure that will enable firms to test new advanced packaging approaches and processes and integrate them into their business models. This infrastructure would otherwise be too expensive and technologically difficult to install and operate independently. This effort is similar to those that Japan has been carrying out to boost its domestic semiconductor industry.
Although the U.S. government has approved a once-in-a-generation investment in advanced manufacturing, NAPMP is only expected to be a first step. Additional policy action will be needed to ensure U.S. leadership in semiconductors. Among other actions, the U.S. can:
- Encourage U.S.-based Packaging: U.S. policymakers can encourage domestic and foreign semiconductor companies to establish new IDM and OSAT packaging facilities in the United States, within the framework of the Semiconductor Financial Assistance Program (SFAP). The SFAP is a $39 billion subsidy program established in CHIPS+ to expand semiconductor manufacturing, research, packaging, equipment, and materials capabilities in the U.S.
- Encourage Diversification of Offshore IDMs: Leading semiconductor companies have already started to diversify their outsourcing contracts beyond China and Taiwan, and the U.S. should encourage additional companies to follow suit. For example, Intel and Foxconn Technology Group have relocated their manufacturing facilities from China to countries like India, Malaysia, and Vietnam.
- Set Packaging Capability Goals: The U.S. should continue to invest in innovation in advanced packaging, set domestic targets for traditional ATP processes, and establish limits on the outsourcing of ATP processes to foreign countries.
- Build Bridges between Government and the Private Sector: An August 2022 NIST report points out that long-term success of the NAPMP will require effective public-private partnerships, easy access to skilled labor and technology, and a flexible intellectual property regime.
- Maintain Long-term Support from the Public: The U.S. government must manage the public’s short-term expectations as well as win long-term support from the public for the NAPMP.
Semiconductor packaging has been outsourced and cultivated abroad in China, Taiwan, and other East Asian countries in the past decades. However, emerging national security concerns and technological innovations in semiconductor packaging have led to a reevaluation of the global semiconductor supply chain, and the importance of innovations in semiconductor packaging for maintaining further improvements in semiconductors. The National Advanced Packaging Manufacturing Program, along with complementary initiatives, can help secure U.S. leadership in semiconductor research and production.
Hideki Tomoshige is a research intern with the Renewing American Innovation project at the Center for Strategic and International Studies in Washington, D.C.
The Perspectives on Innovation Blog is produced by the Renewing American Innovation Project at the Center for Strategic and International Studies (CSIS), a private, tax-exempt institution focusing on international public policy issues. Its research is nonpartisan and nonproprietary. CSIS does not take specific policy positions. Accordingly, all views, positions, and conclusions expressed in this publication should be understood to be solely those of the author(s).